This invention relates to EEPROMs and more specifically to EEPROMs including voltage multiplier circuits.
There are a number of types of EEPROMS available on the market. One such EEPROM is described in U.S. Pat. No. 4,531,203 issued to Masuoka, et al. (incorporated herein by reference) and includes a transistor having a source, a drain, a floating gate, a control gate and an erase gate. During electrical erase, a low voltage is applied to the control gate, the source and the drain, and a high voltage (e.g. about 40 volts) is applied to the erase gate, thereby causing electrons to tunnel from the floating gate to the erase gate. A similar EEPROM is discussed in U.S. Pat. No. 4,561,004, issued to Kuo et al., incorporated by reference.
In other EEPROM transistors, the floating gate is erased by causing electrons to tunnel from the floating gate to the drain. Unfortunately, this requires application of a high voltage (typically 16 to 25 volts) to the transistor drain. The high voltage required for electrically erasing a transistor with a floating gate-erase gate tunneling mechanism or a floating gate-drain tunneling mechanism can be generated from an external voltage source coupled to the EEPROM. Unfortunately, such external voltage sources are expensive and therefore undesirable. To avoid having to provide an external high voltage power supply, it is known to generate the erase voltage on-chip using a voltage multiplier.
A typical voltage multiplier 8 is illustrated in FIG. 1, and includes an input lead 10 for receiving a relatively low input voltage V.sub.IN (e.g. about 5 volts) and an output lead 12 for providing an erase voltage V.sub.OUT (typically 20 to 40V) in response to clock pulse pulses .phi. and .phi.. Circuits such as the one illustrated in FIG. 1 are also known as charge pumps.
The voltage multiplier of FIG. 1 is well known in the art, and is described, for example, in the article by Dickson et al. entitled "On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique," published in the IEEE Journal of Solid State Circuits in June, 1976, incorporated herein by reference.
One problem with voltage multiplier 8 is that transistors 14-1 to 14-N are exposed to and must therefore be capable of withstanding voltages of about 20 to 40V without breaking down. Typical transistors used in LSI integrated circuits include a thin gate oxide (about 250.ANG.) and shallow N+source and drain regions (typically extending to a depth of about 0.3 to 0.4 microns). Application of a voltage in the range of 20 to 40 volts to such transistors typically causes the gate oxide to break down, thereby destroying the transistor, or causes the source-substrate or drain-substrate junction to break down. However, EEPROMs which generate the erase voltage on-chip must include transistors capable of withstanding high voltages. Such high voltage transistors include a thick gate oxide (e.g. in excess of 500.ANG.) and source and drain regions having a deep junction depth (e.g. in excess of 0.7 to 0.8 microns). Unfortunately, such transistors take up a large surface area and are extremely slow. Thus, in the prior art, circuit designers were faced with the option of either having all of their transistors being large and slow, or using special process steps to provide some transistors designed to handle high voltages which were large and slow, and other transistors which did not include a thick oxide and deep junctions. The latter alternative required additional semiconductor processing steps and therefore the resulting devices were complicated and expensive to build.
It is also known in the art to provide circuits for regulating the output voltage provided by voltage multipliers. Unfortunately, such regulating circuits typically control the voltage multiplier output voltage to a value dependent on manufacturing process parameters and temperature. Thus, the erase voltage can vary from production lot to production lot, and can also vary in response to ambient temperature. Thus, despite the presence of the regulator circuit, the output voltage might be either too high (in which case it might stress or damage the transistors in the EEPROM circuit) or too low (in which case it will not erase the EEPROM).